Power amplifiers are often used to amplify wideband signals or signal combinations with high peak to average power ratio, PAR. The amplifiers must then be able to repeatedly output very high power for very short periods, even though the bulk of the output power is generated at the much lower average power level. In systems with random phase combinations of many signals (without any dominating ones) the amplitude of the signal follows a Rayleigh distribution.
A conventional single-transistor power amplifier (for example a class B, AB or F power amplifier) has a fixed radio frequency (RF) load resistance and a fixed voltage supply. The bias in class B or AB amplifiers causes the output current to have a form close to that of a pulse train of half wave rectified sinusoid current pulses. The direct current (DC) current (and hence DC power) is therefore largely proportional to the RF output current amplitude (and voltage). The output power, however, is proportional to the RF output current squared. The efficiency, i.e. output power divided by DC power, is therefore also proportional to the output amplitude. The average efficiency of a power amplifier is consequently low when amplifying signals that on average have a low output amplitude (or power) compared to the maximum required output amplitude (or power), i.e. high PAR.
It is known to have power amplifiers configured to operate in a Doherty mode or a Chireix mode of operation, based on multiple transistors with passive output network interaction and combination. Such power amplifiers are much more efficient than conventional amplifiers for amplitude-modulated signals that have a high peak-to-average ratio (PAR), since they have a much lower average sum of output currents from the amplifier transistors. It will be appreciated that such a reduced average output current leads to high average efficiency.
The reduced average output current is obtained by using two amplifier transistors that influence the output voltages and currents of each other through a reactive output network, the reactive output network also being coupled to the load. By driving the constituent amplifier transistors with suitable amplitudes and phases, the sum of RF output currents is reduced at all levels except the maximum. Also, for these amplifiers the RF voltage at one or both transistor outputs is increased. The reduced RF output currents are essentially obtained by having high transimpedance from at least one transistor to the output, while having the possibility of in-phase combining all transistor outputs to obtain full output power. Reduced average output current means high average efficiency since the DC current is largely proportional to the RF current magnitude.
The field was generalized for two-transistor structures, for example by “Unified High-Efficiency Amplifiers”, published as EP1470635 by the present Applicant. This discloses a 2-stage high-efficiency amplifier with increased robustness against circuit variations, that can avoid tuning of the output network, and with radically increased bandwidth of high efficiency. The amplifier consists in having a longer and a shorter transmission line from two amplifier transistors to a common output (which is coupled to a load, RLOAD). If the most wideband operation is desired, the lengths of the transmission lines are chosen such that the longer line has an electrical length of half a wavelength at center frequency, while the shorter line has an electrical length of a quarter wavelength at center frequency. The basic structure of such an amplifier is shown in FIG. 1.
The amplifier circuit 10 of FIG. 1 comprises a first amplifier 5 located in a first or “main” branch 1 of the amplifier circuit 10 and a second amplifier 6 located in a second or “auxiliary” branch 3 of the amplifier circuit 10. An output of the first amplifier 5 and an output of the second amplifier 6 are coupled to a common output 9 via respective first and second transmission lines 7 and 8. As mentioned above, the first and second transmission lines 7, 8 form a reactive output network which influences the operation of the first and second amplifiers 5, 6. The electrical length of the first transmission line 7 can be designed to be shorter than the electrical length of the second transmission line 8 (for example a quarter wavelength and a half wavelength, respectively, at center frequency, as shown). In operation, an input signal 4 is received by the amplifier circuit 10, split by a signal component separator 2 and amplified by the first amplifier 5 and the second amplifier 6.
The amplifier circuit 10 has a wide bandwidth of high efficiency since the shorter/longer transmission lines 7, 8 of the output network form different kinds of amplifiers at different frequencies. Around a center frequency of operation the amplifier circuit 10 operates as a Doherty amplifier, and at 2/3 and 4/3 of that frequency the amplifier circuit 10 operates as a Chireix amplifier. The wide (about 3 to 1) high efficiency bandwidth is thus achieved in such an amplifier circuit 10 by devising an output network that has both suitable impedance transformation characteristics and full power output capacity over a wide bandwidth, together with a unified control system that allows high efficiency operation at all “modes” across that bandwidth. The amplifier circuit 10 of FIG. 1 therefore allows operation in between and outside the intrinsically narrowband Doherty and Chireix modes.
Further developments of the type of circuit shown in FIG. 1 include three basic expandable multi-transistor structures (and ways to drive them efficiently), for example as disclosed in U.S. Pat. No. 7,221,219 by the present Applicant. Amplifiers such as these, based on passive output network interaction structures, have the advantage of needing only fundamental radio frequency (RF) network and signal modifications.
The reduced average output current mentioned above also comes with a drawback. The RF voltage swing at some transistors is increased, often to the maximum possible. This makes the amplifiers sensitive to resistive losses in a shunt path at the outputs of the transistors, i.e. between the drain and ground, since the loss power is proportional to the RF voltage swing squared. The most common causes of shunt loss are the small series resistance of the capacitance at the drain node, or coupling to a lossy substrate via the drain capacitance (Cds). These capacitively coupled losses often increase almost quadratically with frequency.
Peak power reduction (clipping, crest factor reduction (CFR)) is a method of reducing the peak power of a signal to be transmitted. With conventional single-transistor amplifiers this consequentially increases efficiency. Contrarily, amplifiers such as those described above can, with proper dimensioning, have efficiency almost independent of PAR.
Peak power reduction methods can in some systems reduce the peak power greatly, but while doing so they increase the noise level (EVM) in the signal. This decreases the signal to noise ratio, SNR, of the signal at the receiver, and will thus require a boost in average signal power to compensate for this.
This increase in average power will increase both the DC power drawn and the loss power in the amplifier. For example a commonly found compensatory 1 dB increase in average power increases the DC power drawn by 25% and thus decreases the “equivalent efficiency” to only 80% of the measured efficiency.
It is therefore beneficial to the system to use as little peak power reduction as possible. The ideal solution would be to have the possibility of high peak output power to cope with the peaks of high-PAR signals, while at the same time having high efficiency around the average power level.
Chireix-Doherty amplifiers have the potential of very high average efficiency for signals with high PAR. To achieve this, however, the transistors should have low shunt loss, i.e. resistive loss between the drain and ground nodes. Such transistors are generally more expensive than transistors with high loss. As mentioned above, the most common causes of shunt loss is the series resistance of the capacitance at the drain node, or coupling to a lossy substrate via the drain capacitance (Cds).